1. Field of the Invention
This invention relates to a display device and a driving circuit of the display device. More particularly, this invention relates to an active matrix type display device having thin film transistors formed on an insulating body, and to a driving circuit of the active matrix type display device.
2. Description of the Related Art
The progress of miniaturization in semiconductor fabrication technologies has in turn brought forth miniaturization of LSI. As the application of such miniature LSI to small appliances such as hand-held terminals has made a progress, lower power consumption has now become a requisite. Therefore, LSI of a low voltage driving type such as 3.3 V has become predominant at present. In LCD (Liquid Crystal Display) the demand for which has been remarkably increasing nowadays in the application as a monitor for hand-held terminals and computers, on the other hand, driving of the liquid crystal is made by signals having a voltage amplitude of 10V to 20V in most cases. Therefore, at least a circuit portion driven at a high power source voltage corresponding to this driving circuit coexists. For this reason, it is essentially necessary to connect the controller LSI driven at the low voltage described above and the liquid crystal driving circuit driven at the high power source voltage by a level shifter that changes the voltage amplitude of signals.
Besides the LCD, displays using electroluminescence devices (which will be hereinafter called “EL devices” and define both single-term emission and triple-term emission as EL) have been developed recently, and the requirement for low power consumption is also strong in this field.
FIG. 9 of the accompanying drawings illustrates an example of a source signal line driving circuit of the display device. Here, a start pulse, a clock signal, a digital image signal, etc, are those signals that are inputted from outside the display device. Since these signals are supplied from the controller LSI described above, the voltage amplitude is generally low voltage amplitude of 3.3 V, or the like. Therefore, in the driving circuit shown in FIG. 9, the digital image signal is subjected to voltage amplitude conversion (level conversion) by a level shifter 905 immediately after it is inputted. The signals inputted from the external controller LSI such as the clock signal and the start pulse are likewise subjected to level conversion though not specifically shown in the drawing.
The circuit operation will be explained. The shift register 901 outputs pulses in accordance with the clock signal and the start pulse, and the pulses of two adjacent stages are inputted to a NAND circuit 903. The NAND circuit 903 outputs a pulse having a low (Lo) potential from its output terminal only when a pulse having a high (Hi) potential is inputted to both of two-input terminals. After passing though a buffer (abbreviated as “Buf.”) of a subsequent stage, the pulse changes to a first latch pulse. The pulse is then inputted to a first latch circuit 906. The digital image signal subjected to level conversion by the level shifter 905 is latched in accordance with the input timing of this first latch pulse. After this latch operation is conducted from the first stage to the final stage, the second latch pulse is inputted to a terminal 19 within a retrace line period, and the digital image signals for one horizontal period that are held by the first latch circuit 906 are altogether transferred to the second latch circuit 907. Thereafter, a gate signal line writes signals to pixels of the selected row to display the images.
FIGS. 10(A), 10(C) and 10(D) show an example where the level shifter 905 shown in FIG. 9 is constituted by a conventional level shifter. When voltage amplitude of the input signals (In, Inb) is as small as about 3.3 V, the level shifter having such a construction sometimes fails to normally conduct level conversion owing to influences of the threshold values of the TFT constituting the level shifter.
Therefore, a level shifter having a construction shown in FIGS. 10(B) and 10(E) to 10(H) is employed. The level shifter shown in FIGS. 10(B) and 10(E) to 10(H) conducts level conversion by means of a differential amplifier, and can accomplish a reliable level conversion function even when voltage amplitude of the input signals is small. Therefore, this is an extremely effective circuit for achieving low voltage driving of the circuit. The level shifter using the differential amplifier is disclosed in Japanese Patent Application No. 2000-193498.
On the other hand, the level shifter shown in FIGS. 10(B) and 10(E) to 10(H) needs a current source. In other words, since a constant current is always supplied during driving of the circuit (regardless of driving or stop of the level shifter), this current impedes low power consumption of the display device as a whole.
Lowering of the driving voltage of the driving circuit, etc, is originally directed to achieve low power consumption with the progress of hand-held terminals, etc, and it is technically meaningless if the circuit purposely employed to lower the driving voltage increases power consumption.